The electronic control unit in which the main control circuit section and the combination control circuit section are connected with each other in series and work together is widely used in practice. However, one of functions of the combination control circuit section is to use the minimum number of input/output terminals in the main control circuit section which are limited to terminals requiring high-speed processing to thereby compensate insufficient additional input/output signals in low-speed operations by interposing the combination control circuit section which is connected in series in response to various applicable vehicle types. Therefore, input/output signals indirectly connected from the combination control circuit section to the main control circuit section are limited to signals in low-speed operations in which response delay with respect to the transmission of input/output signals does not matter. Another one of functions of the combination control circuit section is to constantly monitor the operation state of the main control circuit section. The monitoring control is devised to be performed at relatively lower frequency as compared with the frequency of uplink and downlink communication for reducing a control burden in the main control circuit section.
For example, in FIG. 1 and FIG. 2 of the following Patent Literature 1 “ONBOARD ELECTRONIC CONTROL UNIT WITH MONITOR CONTROL CIRCUIT”, a main control circuit section 20A mainly configured by a microprocessor 20 and including a multi-channel AD converter 26 performs serial communication of a downlink communication data DND and an uplink communication data UPD with a monitor control circuit section 30A (corresponding to the combination control circuit section) mainly configured by a logic circuit section 30a and including a multi-channel AD converter 36 through serial interface circuits 27a, 37a, performing drive control of a first electrical load group 12a which is directly driven and a second electrical load group 12b which is indirectly driven in accordance with operation states of a first input sensor 11a as a direct input sensor including an opening/closing sensor and an analog sensor and a second input sensor 11b as an indirect input sensor. The monitor control circuit section 30A sends question data as the uplink communication data UPD, determining presence of an abnormality in the main control circuit section 20A by comparing answer data from the main control circuit section 20A obtained as the downlink communication data DND with correct answer data stored in the monitor control circuit section 30A. The downlink communication data DND shown in FIG. 2 is, for example, 100-bit, the uplink communication data UPD is, for example, 500-bit, and a communication permission period T0 is, for example, 5 msec, but full-duplex block communication is performed, in which a period of time necessary for one communication is, for example, 0.5 msec or less.
In contrast, for example, in the following Patent Literature 2 “FRAME CONFIGURATION OF CYCLIC TRANSMISSION”, a concept for shortening the communication period while mixing high-speed communication data and a low-speed communication data is disclosed. In FIG. 1, S1 denotes a start mark STX of communication, S2 denotes a high-speed data block, S3 denotes an address block, S4 denotes a low-speed data block corresponding to a transmission destination designated by the address block S3, S5 denotes an end mark ETX of communication and S6 denotes an additional block for checking an error with respect to transmission data. A data frame Fi (i=1, 2 . . . ) including the block S1 to S6 is sequentially transmitted from a driven control unit 2 in FIG. 2 to a control sequencer 1 by every 2 msec. A storage location of the high-speed data S2 is, for example, a fixed address storage unit 12 of 32 words, whereas, the low-speed data S4 is transmitted to, for example, a storage unit 13 of 20×32 words as a storage location while sequentially updating the address. Therefore, according to the divided transmission method, a period of time necessary for transmitting the high-speed data of 32 words is reduced to 2/21 as compared with a case of transmitting data of 21×32 words at a time.
On the other hand, in FIG. 1 to FIG. 3 of the following Patent Literature 3 “A/D CONVERTER” relating to the above invention, there is disclosed a concept in which one of 8 analog signals CH0 to CH7 inputted from an analog input terminal 1 in FIG. 1 is selected by a multiplexer 2 in an analog/digital converter 10 to be inputted into an A/D converter 4 and digitally converted, and an externally attached decode circuit 11 (FIG. 2) becomes valid by an extended channel selection signal 6, and one of eight extended analog signals CH20 to CH27 inputted from an extended analog signal input terminal 12 is selected and inputted to the A/C converter 4 through an input channel CH0 to thereby extend the channels so that the total 15 analog signals can be dealt with. The multiplexer 2 is controlled by selection data bits b0 to b3 serial-transmitted by a channel selection register 20 (FIG. 3), and the analog/digital converter 10 supplies parallel signals of the bits b0 to b3 to the externally attached decode circuit 11.
Patent Literature 1: JP-A 2009-129267 (FIG. 1, Abstract, FIG. 2, paragraphs 0034 to 0036)
Patent Literature 2: JP-A5-244218 (FIG. 1, Abstract, paragraph 0007)
Patent Literature 3: JP-A8-307269 (FIG. 1, Abstract, paragraph 0028)